A Low-Power Circuit Technique for Dynamic CMOS Logic
نویسندگان
چکیده
Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipation with almost same noise immunity compared to the recently proposed circuit techniques for dynamic logic styles to improve noise immunity. The concept is validated through extensive simulation. Keywords-Domino logic, dynamic logic, power consumption, leakage tolerance, robustness.
منابع مشابه
Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology
The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...
متن کاملA New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CM...
متن کاملDesign of Mt-cmos Domino Logic for Ultra Low Power High Performance Ripple Carry Adder
As the requirement of low power high performance arithmetic circuits, in this paper we introduced a design of new MT-CMOS domino logic and FTL dynamic logic technique to design adder circuit. The MT-MOS transistors reduce the power dissipation by minimizing sub threshold leakage current in domino logic circuits introduced. The MT-NMOS transistor connected in discharging path of output inverter ...
متن کاملDesign and Analysis of Conventional CMOS and Energy Efficient Adiabatic Logic for Low Power VLSI Application
In recent years, low power circuit design has been an important issue in VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. energy. This paper proposes an Adder circuit based on energy efficient two-phase clocked adiabatic logic. A simulative investigation on the proposed 1-bit ful...
متن کاملLow-Power Adder Design for Nano-Scale CMOS
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
متن کامل